How can I set the DFE (Decision Feedback Equalization) in Adaptive Mode for the 10G transceivers inside Cyclone 10 GX?
Hi All, Did anybody have any experience with setting up the DFE (Decision Feedback Equalization) for the 10G transceivers inside the Cyclone 10GX? The easy way to set the analog parameters for sign...
Hi Bogdan,
Now I am confused as well due to discrepancy of info around. :)
I suspect this is due to earlier version of Quartus bug that they forgot to disable the DFE setting but then Quartus disable DFE and fix it in later Quartus version.
In latest Quartus version like v19.1 pro edition, NativePHY IP no longer show DFE setting and you also can't find the DFE register mapping in c10-registermap.xlsx
May I know which Quartus version that you are using ?
I will also try to check internally within Intel FPGA to clarify on the DFE support plan for Cyclone 10.
Thanks.
Regards,
dlim
Hi Deshi,
That explains why we see different things ☺ … indeed, my version is 18.0 pro edition build 219 … or at least the one that I have in the lab on the laptop used for TTK experiments.
Yes, it would be good to find out what DFE support plans Intel has. Also, if the TTK, the PHY IP gen and the Assignment Editor in our version set some values for the DFE taps, can we really count that these taps are really set? In other words, can you please provide the Cyclone 10 GX register map prior to removing the DFE registers in your rev 19.1? These DFE values must go somewhere. So, we need to know those registers, in order to turn ON that DFE Adaptive mode using the register set (i.e., implement the procedure described for Arria 10, but using the Cyclone 10GX DFE registers).
Many thanks, once again.
Bogdan
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