Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

How can I make comunication between dsp and Dual-Port Ram internal FPGA?

I want to comunicate dsp with Dual-Port Ram internal FPGA.Because there are two Dual-Port Ram in FPGA, and one to read,the other one to write.Now the databus is bidirectional,so I must transform the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

In your process (Which is an Asynchronous process) the signals DATAbus and Data1 and IOCS_N are not assigned on all paths though the logic. This will infer storage (Latches). I imagine this is not what you intend.

i.e. what is the value of RAM1EN when Address is all ones?

I suggest you either rewrite your code as a synchronous process or if you just want combinatorial logic then ensure all signals are assigned in all paths