Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
Sounds like you're trying to assign a std_logic_vector to a bit vector. They are not the same thing.
otherwise, sounds like you're doing it correctly. my_other_vector <= sec_vector(3 downto 0); - Altera_Forum
Honored Contributor
my error sorry
- Altera_Forum
Honored Contributor
type missmatch