HOW CAN I FIX MY DDR_CALIB_FAIL ?

HI,

Thanks for providing detail diagram drawing. This is good in analyzing issue debug.

FYI... DDR3 calibration only rely on operation between UNIPHY IP and on board DDR3 SDRAM.

• The rest of your user design logic won't affect DDR3 calibration operation.
• Your own user logic design only matter on DDR3 actual write/read operation that happened once DDR3 calibration is passed

Therefore, I suspect DDR3 calibration failure could be due to either

• FPGA IOPLL clocking is not clean (too jittery) as you are now using single PLL to clock multiple design block. For debug sake, you can try to use another additional PLL to clock your own user logic. See if it makes any difference
• Another possibility is maybe something screw up during your Quartus design integration. You may want to cross check with original passing design to see if there is any mess up on UNIPHY IP setting (try regenerate the IP again), UNIPHY DDR3 connection on top level design and also verify DDR3 IO setting in Quartus *.qsf file.

Thanks.

Regards,

dlim

Hi,

Firstly, thank you for your attenition.

I have tried the configuration on scheme, but it didn't work.

I'm also adding the screenshots of DDR settings.

Best,

Veysel.

Hi Veysel,

I am not worry about the DDR3 setting now as you used the same DDR3 setting and it passed calibration in original design, right ?

Your goal now is to take the calibration failing design and gradually remove additional design block one by one to make it more alike to original passing design.

Then eventually you will figure out which part of the design is causing the problem here.

Regards,

dlim

Hi Veysel,

I have not hear back from you for 2 months. Hopefully my debug suggestion help out and you are able to make progress with your project.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim