HI,
Thanks for providing detail diagram drawing. This is good in analyzing issue debug.
FYI... DDR3 calibration only rely on operation between UNIPHY IP and on board DDR3 SDRAM.
- The rest of your user design logic won't affect DDR3 calibration operation.
- Your own user logic design only matter on DDR3 actual write/read operation that happened once DDR3 calibration is passed
Therefore, I suspect DDR3 calibration failure could be due to either
- FPGA IOPLL clocking is not clean (too jittery) as you are now using single PLL to clock multiple design block. For debug sake, you can try to use another additional PLL to clock your own user logic. See if it makes any difference
- Another possibility is maybe something screw up during your Quartus design integration. You may want to cross check with original passing design to see if there is any mess up on UNIPHY IP setting (try regenerate the IP again), UNIPHY DDR3 connection on top level design and also verify DDR3 IO setting in Quartus *.qsf file.
Thanks.
Regards,
dlim
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