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It should be noted that there is a big difference between NON POWERED and HOT SOCKETING.
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Nevertheless, the device handbook is discussing
power sequencing under the
hot socketing chapter. That's plausible to my opinion, cause hot socketing is relying on the same I/O cell features as power sequencing.
Thus I'm pretty sure, that the quoted leakage specification (I omitted the dynamic current specification) also applies to the discussed case. The hot-socketing case doesn't make any assumption regarding order and timing of the sequential connection of signals, in so far it's the worst case that must be expected to include all power sequencing cases.
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I recall that there is a note somewhere mentioning that if the Vccio of the bank the pins are located in is NOT powered, then the leakage current may be considerably higher.
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Yes, obviously is 300 uA higher than 10 uA leakage specification in normal operation.