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Altera_Forum
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14 years ago

Hold time is not satisfied

I created a project with sopc builder，it included nios ii、pipeline bridge、ddr2 controller、onchip memory and a module i writed。The clock was used the ddr2‘s sysclk&#...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi

I think you can specify the set_min_delay between the path

GE_sopc_inst|the_ddr2|ddr2_controller_phy_inst|ddr 2_phy_inst|

ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout

to remove the hold time violation