Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hold time is not satisfied

I created a project with sopc builder,it included nios ii、pipeline bridge、ddr2 controller、onchip memory and a module i writed。The clock was used the ddr2‘s sysclk。After compilation,a critical warning occured,the hold time is not satisfied, GE_sopc_inst|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|

ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].

clk_div_slave|clkout -0.013

How can i solve this problem?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi

    I think you can specify the set_min_delay between the path

    GE_sopc_inst|the_ddr2|ddr2_controller_phy_inst|ddr 2_phy_inst|

    ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout

    to remove the hold time violation