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Altera_Forum's avatar
Altera_Forum
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13 years ago

High speed >3 ghz clock in FPGA

I am very new to FPGAs and to this forum, but I'm hoping for some help reading between the lines in some recent literature on an optical phase-lock-loop using FPGA. I am too new to post a link, but my hope is to get some help interpreting the following statements from the paper:

"we have chosen Altera EP2C8Q208C FPGA as the core chip for the controlling circuit. Its general clock speed can be up to 50–100 MHz and a high speed clock of several GHz can be generated, which is a key factor for digital loop filter."

and

"an equivalent 3.5 GHz clock has been realized by an additional function embedded in FPGA chip."

I believe the chip they are using is a cyclone II chip but I am not familiar with what "additional function" the authors may be referring to. Can anyone help me understand how they have created a 3.5GHz clock within the FPGA. Beyond that, my next question would be to find out if my DE0-nano (Cyclone IV) board could do the same thing.

Any help is greatly appreciated!

-Andy

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The clock tree of Cyclone FPGA family is restricted to about 400 MHz. Considerable higher clock frequencies are supported by Gigabit transceiver blocks (e.g. in Cyclone IV GX), but not available for general logic processing.

    Higher effective timing resolution can be achieved by double data rate und multi-phase techniques. Without details it's hard to guess what the quoted paper is referring to.