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Altera_Forum
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13 years ago

High speed >3 ghz clock in FPGA

I am very new to FPGAs and to this forum, but I'm hoping for some help reading between the lines in some recent literature on an optical phase-lock-loop using FPGA. I am too new to post a link, but m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The clock tree of Cyclone FPGA family is restricted to about 400 MHz. Considerable higher clock frequencies are supported by Gigabit transceiver blocks (e.g. in Cyclone IV GX), but not available for general logic processing.

Higher effective timing resolution can be achieved by double data rate und multi-phase techniques. Without details it's hard to guess what the quoted paper is referring to.