High clock skews

Hi guys another help required..

Although i know about clock skew..but with respect to quartus reports its a bit confusing

I am working with 225 Mhz ie 4.444 ns clock and in the report for reg to out setup i am having clock skews of -4.5ns.

_ve clock skews are generally because the receiving reg is getting the clock earlier than the transmitting (pls do comment if i am wrong)

so my question is that a high -ve clock as such at module level can be optimized using synthesis techniques or the rtl files need a change...And really if someone can tell me more about clock skews and their behaviour i will be really grateful

I am attaching the reg to out rpt if in case i missed anything