High bandwidth data transfer between hps and fpga

Since you are connecting it to the FPGA IO, I assume that you've created a "PIO" Qsys component and connect the HPS-FPGA bridges to it. The HPS-FPGA bridge is not really efficient for such scenarios (it works better when connected to a FPGA master that requires wide data width). Perhaps it would be better to see if the FPGA IO can be controlled using IP within the FPGA, and use the HPS-FPGA lightweight bridge to update/change the registers for the FPGA IP.