Forum Discussion
Altera_Forum
Honored Contributor
9 years agoIn this example
https://rocketboards.org/foswiki/view/projects/datamover it looks like the transfer from FPGA to HPS bridges are happening at 133MHz (multiply that with 128-bit, so 2.1GB/s assuming that the pipeline can be saturated) It you just wanted to access the HPS SDRAM and do not need coherency, you can use the FPGA-to-SDRAM bridge instead - here's an example implementation: https://rocketboards.org/foswiki/view/projects/cyclevsocsdramperformanceexampledesign Hope this helps...