Hi, How to choose the speed grade in an FPGA or CPLD?

Hi

I've a lot of questions about FPGAs and CPLDs speed grade, I want to generate a pulse of 3 ns acording to an event, which means that I need at least a 333 MHz clock, either external or using a PLL, right?

I don't understand the definition of speed grade, I found than means that an FPGA speed grade -10 for example, has a delay of 10 ns through macrocell, how this affect the maximum frequency supported? In the forum said that it depends of what I want to implement, I don't understand this either

Also, if I have an FPGA speed grade -6 (I read in a post that means 315 MHz) can I use an external clock of 300 MHz and try to obtain a higher frequency? the speed grade has to suport this new frequiency?

Speed grade definitions are equal in FPGAs and CPLDs?

If I don't need very much processing, only sample of events and generate pulses (3 ns), how can I decide which FPGA or CPLD buy?

Where can I find more information in order to undestand FPGAs an CPLDs work frequency?

I know that there are a lost of questions, I hope you can help me, thank you so much.