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Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi, How to choose the speed grade in an FPGA or CPLD?

Hi I've a lot of questions about FPGAs and CPLDs speed grade, I want to generate a pulse of 3 ns acording to an event, which means that I need at least a 333 MHz clock, either external or u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I want to generate a pulse of 3 ns according to an event

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What is the requirement for the timing relationship between the event and the pulse?

What is the logic level of the signal you are interfacing to, and what is the logic level of the pulse supposed to be?

The highest speed outputs on FPGAs are the LVDS and transceiver transmitter outputs. FPGA LVDS output signals can operate up to 800Mbps in the Cyclone devices, and the transceivers can operate at higher frequencies. Using these outputs, the speed grade becomes less of an issue.

Cheers,

Dave