Hi guys, I have a question about ADC sampling using Cyclone IV.

The data rata of ad output(ad_in2) is 700Mbps together with the DDR data bit clock(350MHZ) and frame clock(50MHZ). Its sampling resolution is 14 bit.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.macro_def.all;
-------------------------------------------------------------
entity ad_control is 
 port(
   clk_in    : in std_logic;--50MHZ
   rst     : in std_logic;
   ad_dco    : in std_logic;--350MHZ
   ad_fco    :  in std_logic;--50MHZ
   ad_in2    : in std_logic;--700Mbps
 
   ac_in2    : out std_logic_vector(AD_WIDTH-1 downto 0)
   );
end entity ad_control;
-------------------------------------------------------------
architecture arch_ad_control of ad_control is
 ---------------------------------------------------------
 --the declaration of module pll
 
 component pll is
  port(
    inclk0   : in std_logic := '0';
    c0    : out std_logic
   );
 end component;
 
 --output signals
 signal  clk    : std_logic;
 
 ---------------------------------------------------------
 --the declaration of module ad_pll
 
 component ad_pll is
  port(
    inclk0   : in std_logic := '0';
    c0    : out std_logic
   );
 end component;
 
 -- output signals
 signal  dco_clk   : std_logic;
 
 ---------------------------------------------------------
 --the declaration of module ad_ddio_in
 
 component ad_ddio_in is
  port(
    datain   : in std_logic_vector(0 downto 0);
    inclock   : in std_logic;
    dataout_h  : out std_logic_vector(0 downto 0);
    dataout_l  : out std_logic_vector(0 downto 0)
   );
 end component;
 --output signals
 signal  ad_in2_h  : std_logic_vector(0 downto 0);
 signal  ad_in2_l  : std_logic_vector(0 downto 0);
 
 ---------------------------------------------------------
 --the declaration of module ad_fifo
 
 component ad_fifo is
  port(
    data   : in std_logic_vector(AD_WIDTH-1 downto 0);
    rdclk   : in std_logic;
    rdreq   : in std_logic;
    wrclk   : in std_logic;
    wrreq   : in std_logic;
    q    : out std_logic_vector(AD_WIDTH-1 downto 0)
   );
 end component;
 
 --input signals
 signal  ad_fifo_wr  : std_logic;
 signal  ad_fifo_rd  : std_logic;
 
 ---------------------------------------------------------
 --internal signals
 
 signal  ad_in2_tmp  : std_logic_vector(0 downto 0);
 signal  ac_in2_tmp  : std_logic_vector(AD_WIDTH-1 downto 0);
 
 signal  ad_fco1   : std_logic;
 signal  ad_fco2   : std_logic;
 ---------------------------------------------------------
 
begin
 
 ---------------------------------------------------------
 --ad_pll instance
 
 inst_pll: pll
 port map(
    inclk0 => clk_in, 
    c0 => clk--50MHZ
   );
 
 ---------------------------------------------------------
 --ad_pll instance
 
 inst_ad_pll: ad_pll
 port map(
    inclk0 => ad_dco, 
    c0 => dco_clk--350MHZ
   );
 
 ---------------------------------------------------------
 --ad_ddio_in instance
 
 ad_in2_tmp(0) <= ad_in2;
 inst_ad_ddio_in: ad_ddio_in
 port map(
    datain => ad_in2_tmp, 
    inclock => dco_clk, 
    dataout_h => ad_in2_h, 
    dataout_l => ad_in2_l
   );
 
 ---------------------------------------------------------
 --serdes conversion
 
 process(dco_clk, rst)
 begin
  if(rst = '1') then 
   ac_in2_tmp <= (others => '0');
  elsif(rising_edge(dco_clk)) then 
   ac_in2_tmp <= ac_in2_tmp(AD_WIDTH-3 downto 0) & ad_in2_l & ad_in2_h;
  end if;
 end process;
 
 ---------------------------------------------------------
 --synchronize the ad data
 
 process(dco_clk, rst)
 begin
  if(rst = '1') then
   ad_fco1 <= '0';
   ad_fco2 <= '0';
  elsif(rising_edge(dco_clk)) then
   ad_fco1 <= ad_fco;
   ad_fco2 <= ad_fco1;
  end if;
 end process;
 
 ad_fifo_wr <= ad_fco1 and (not ad_fco2);
 ad_fifo_rd <= '1';
 
 inst_ad_fifo: ad_fifo
 port map(
    data => ac_in2_tmp, 
    rdclk => clk, 
    rdreq => ad_fifo_rd, 
    wrclk => dco_clk, 
    wrreq => ad_fifo_wr, 
    q => ac_in2
   );
 
 ---------------------------------------------------------
end architecture arch_ad_control;