Hey, I would like to use HyperBus memory. My board will contain cyclone V too. My question is, how the clock pin in the HyperBus should be connected? To a standard IO of the FPGA or to a dedicated CLK pin. Best regards, Peleg

link to the HyperBus:

https://www.cypress.com/products/hyperbus-memory

Hello ,

Sorry somehow i missed your questions .

Can I know which cyclone V part number ? Can I know who is driving the clk ? if FPGA it will be good to connect to clock output .

Also are you using IP to map the hyperbis memory ? or your own RTL ?

Thank you,

Regards,

Sree