First ... have you read this..?
http://www.altera.com/literature/an/an458.pdf Here are some things to know:
1 - The bootloader will expect to see a valid FPGA image at the beginning of the flash. It will read some bits within the FPGA image to determine how long it is. It then jumps to the end of the FPGA image where it expects to see a valid NIOS software image.
2 - The flash programmer programs the FPGA image into flash. It then calculates how long the image is and programs the software file (ELF) at the address immediately following the FPGA image.
The problem is that the bootloader truly only works at the base address of the flash (first image location). So you've got two problems you need to solve...
1 - How are you going to load multiple SOF+ELF images at different addresses in the EPCS flash?
2 - Once you've got those images loaded, how are you going to select from and boot them?
. I'll work backwards starting with the bootloader issue. I had to modify the existing bootloader to get it to do what I needed it to do. Since you are going to have to modify the bootloader you can kind of choose how you want things to work. For example, you could completely move away from the scheme where the ELF image follows the SOF image in memory and you could place the ELF images somewhere else in the flash.
. What I chose to do was leave the SOF+ELF files combined and simply change the address of where the bootloader begins looking for the images depending on which image I was running. I only one application image and one safe image.
. The source code for the EPCS bootloader can be found in:
C:\altera\81\nios2eds\components\altera_nios2\boot_loader_sources Once you've modified and compiled your new bootloader, you can go into Quartus and override the memory initialization file for the boot RAM inside the EPCS module inside your SoPC system and make it use your compiled MIF instead.
Now on to the file creation. You can use the IDE but I think that's going to be more difficult. It's easier to script things. Here are snippets from my scripts:
# Creating .flash file for the FPGA configuration
echo Creating firmware flash file ...
"$SOPC_KIT_NIOS2/bin/sof2flash" --epcs --compress --input="../altera/top.sof" --output="firmware.flash"
# Creating .flash file for software code
echo Creating safe and application flash files ...
"$SOPC_KIT_NIOS2/bin/elf2flash" --epcs --after="firmware.flash" --input="../software/top/Release/top.elf" --output="app.flash"
# Convert to binary
echo Converting flash files to binary ...
nios2-elf-objcopy -I srec -O binary firmware.flash firmware.bin
nios2-elf-objcopy -I srec -O binary app.flash app.bin
# Concatenate
echo Concatenating binary files to create final programming file ...
cat firmware.bin app.bin > app_image.bin
The final file "app_image.bin" is simply a binary file. You can then program this file into any location in the EPCS flash. You can use the IDE flash programmer to do this or whatever means you are providing in your application to remote download.
Sorry, I know this is probably a rough overview of a lot of information but I hope it points you in the right direction. Read the referenced document.
Jake
Honored Contributor
