Altera_ForumHonored Contributor11 years ago[HELP!!!!]anyone can give me a design example of ddr2 controller in Cyclone IV Eddr2 controller of altmemphy ddr2:MT47H32M16-25E FPGA:Cyclone IV EP4CE40F23C8 I don't know how to configure the time parameter of ddr2 controller.
Recent DiscussionsCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File Information