Forum Discussion
SparkyNZ
Contributor
ContributorHelp with VJTAG and TCL script
I must be doing something really stupid here. The problem I have is that I seem to have a disagreement between instruction register values in TCL script and in Verilog. In TCL: set RESET_HI_...
YuanLi_S_Intel
Regular Contributor
Regular ContributorI am glad it is solved now.
Meanwhile for the TCK frequency, it affects the speed of communication using JTAG. You may put higher frequency to increase the speed. However, too high will cause communication issue as well. You can try and find the optimum speed for your case.
