Forum Discussion

Occasional Contributor

2 years ago

Help with constraining source synchronous and system synchronous combination

Hello, I have the following system that is sadly not modifiable anymore : The pin names are the same as the 'signal' names. So what we have is an FPGA that is clocked by the REF_CLK, which g...

Configuration

Generic Io

KennyT_altera

Super Contributor

2 years ago

Not sure if you have further question on this? If no, we shall close this thread.

Forum Discussion

Help with constraining source synchronous and system synchronous combination

Recent Discussions

EP4CE22F 256 net length report not found

Quartus Prime that automates the task We're building a complex SoC design targeting an Agilex 7 device and need to integrate multiple IP cores with custom logic. What is Quartus Prime Platform Designer, and what are its key capabilities for system-level integration?

Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY_FA

Cyclone V SE Pulldowns on QSPI I/F. Why?

Stratix III FPGA Development Kit