help with coding 4bit adder on vhdl

I've been having trouble with coding this simple full adder on VHDL with structural coding more specifically using components

and here's my code :

Library ieee;
use ieee.std_logic_1164.all;
 
Entity 4bfa is
port(     A : In std_logic_vector (3 downto 0);
              B : In std_logic_vector (3 downto 0);
              cin : in std_logic;
	      cout: out std_logic;
	      Sum   : out std_logic_vector (3 downto 0) );
end 4bfa;
 
architecture my of 4bfa is 
cin := 0;
signal     c0,c1,c2,c3,s1,s2,s3,s4 : std_logic;
 
component fastructural is 
 port (      I1,I2, ci: IN std_logic;
                 co,s     : out std_logic);
end component;
 
begin
 
u1 : fastructural port map( I1 => A(0),
                                                  I2 => B(0),
						  ci =>cin,
						  co=>c0,
						  s=>s1);
u2 : fastructural port map( I1 => A(1),
                                                  I2 => B(1),
						  ci =>c0,
						  co=>c1,
						  s=>s2);
									  
u3 : fastructural port map( I1 => A(2),
                                                 I2 => B(2),
						 ci =>c1,
						 co=>c2,
						 s=>s3);
u4 : fastructural port map( I1 => A(3),
                                                  I2 => B(3),
						  ci =>c2,
						  co=>c3,
						  s=>s4);
 
cout<=c3;
 
Sum<="s4&s3&s2&s1";
 
end my;

and he is the errors that I get :

Error (10500): VHDL syntax error at 4bfa.vhd(4) near text "4";  expecting an identifier
 
Error (10500): VHDL syntax error at 4bfa.vhd(11) near text "4";  expecting an identifier

Also for the fastructural componant is a componant of a full adder for one bit that I already have on another VHDL code and that works just fine.

but I still don't know what is the issue.