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Altera_Forum
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13 years ago

Help with CIC decimation filter

Hi, I wrote a Verilog code for a CIC decimation filter. I relied on a code written in the book 'digital signal processing with FPGA' . Here is the code: // cic decimation filter : R=64, M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I tried the following change and got rid of red undefined states:

i0 <= i0 + {{16{x[7]}},x_in}; //sx;

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hmm, that did not change anything for me. I simply replaced i0 <= i0 + sx by i0 <= i0 + {{16{x[7]}},x_in} , but the result is still the same.