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Altera_Forum
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13 years ago

Help with CIC decimation filter

Hi, I wrote a Verilog code for a CIC decimation filter. I relied on a code written in the book 'digital signal processing with FPGA' . Here is the code: // cic decimation filter : R=64, M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I don't remember verilog well but just a thought, you need to insert reset in the sensitivity list as the clock

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Not really. It is not a must. I never used the reset in the sensitivity list in my old codes and they all worked normally.