Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHelp with CIC decimation filter
Hi, I wrote a Verilog code for a CIC decimation filter. I relied on a code written in the book 'digital signal processing with FPGA' . Here is the code: // cic decimation filter : R=64, M...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I don't remember verilog well but just a thought, you need to insert reset in the sensitivity list as the clock --- Quote End --- Not really. It is not a must. I never used the reset in the sensitivity list in my old codes and they all worked normally.
