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Altera_Forum's avatar
Altera_Forum
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13 years ago

Help with CIC decimation filter

Hi, I wrote a Verilog code for a CIC decimation filter. I relied on a code written in the book 'digital signal processing with FPGA' . Here is the code: // cic decimation filter : R=64, M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I have been struggling in the past 4 days to get this to work and so far it is only getting worse. For instance :

always @(posedge clk)begin

if(reset) begin

i0 <= 24'd0;

i1 <= 19'd0;

i2 <= 14'd0;

x <= 8'd0;

simulation shows only x is becoming 0 when reset is high. The other have the status x from the beginning. Plus modelsim seems to have a problem updating my files from time to time, it kind of stores an older version of each file and uses it, whenever it feels like it. I'm so frustrated right now