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Honored Contributor
Honored ContributorHelp using verilog files in Quartus
Hi, I’m a beginner using FPGAs and also programming in Verilog or VHDL. I have two Verilog files created in the same Quartus 9.0 project, lets say file A and file B. File B finishes a process tha...
Altera_ForumHonored Contributor
Honored ContributorIt should be possible to use the `include command. `include the file you want to use and then compile only the top file.
-Vinay
