Help on VHDL

Thanks a lot. that is really the problem. I got the idea.

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Rewrite the process this way:

process (reset, cp, q)

begin

if (reset = '0')

q <= 0;

elsif (cp'Event AND cp='1') Then

if (q > 11) Then

q <= 0;

else

q <= q + 1;

endif;

end if;

end process;

Otherwise the q>11 condition would be synthesized with combinatorial logic and it will lead to impredictable behaviour on real hardware, since q bits don't switch at the same time.

For example, from 7 (binary 0111) to 8 (1000) you can have a transitional status like 1111 or 1101, which is >11 and would reset your counter.

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