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Altera_Forum's avatar
Altera_Forum
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14 years ago

Help on VHDL

Just want to design a mod-12 counter counting from 0 to 12, but when I use the following code, it always set q as 0 to 7 instead of 0 to 11 (Under QSim simulator). ================================...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Rewrite the process this way:

process (reset, cp, q)

begin

if (reset = '0')

q <= 0;

elsif (cp'Event AND cp='1') Then

if (q > 11) Then

q <= 0;

else

q <= q + 1;

endif;

end if;

end process;

Otherwise the q>11 condition would be synthesized with combinatorial logic and it will lead to impredictable behaviour on real hardware, since q bits don't switch at the same time.

For example, from 7 (binary 0111) to 8 (1000) you can have a transitional status like 1111 or 1101, which is >11 and would reset your counter.