[Help on VHDL] FATAL ERROR while loading design

Thanks for the help Tricky! I got it working now.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftreg is port (
        A: in std_logic; -- data in
        B: in std_logic;
        clk: in std_logic; -- Clock
        clr: in std_logic; -- Clear
        preset: in std_logic; --Preset
        q : out std_logic_vector(3 downto 0) -- output Q
);
end;
architecture rtl of shiftreg is
signal q_int : std_logic_vector(3 downto 0);
begin
    process (clk, clr,preset)
     begin
        if (preset='0') then
            q_int <= "1111";
        elsif (clr='0') then
            q_int <= "0000";
        elsif (clk'event and clk = '1') then
            q_int(0) <= A and B;
            q_int(1) <= q_int(0);
            q_int(2) <= q_int(1);
            q_int(3) <= q_int(2);
        end if;
    end process;
   q <= q_int;
   
end rtl;

Library IEEE;
Use IEEE.std_logic_1164.all;
Entity shiftregTB is
end;
Architecture rtl of shiftregTB is
    signal A,B,clk,clr,preset: std_logic;
    signal q,q_int :  std_logic_vector(3 downto 0);
begin
UUT : entity work.shiftreg port map(A,B,clk,clr,preset,q_int);
     
tb : process
begin
    preset<='0';
    wait for 10 ns;
    preset<='1';
    wait for 10 ns;
    clr<='0';
    wait for 20 ns;
    clr<='1';
    wait for 20 ns;
    clk<='1';
    wait for 20 ns;
    A<='1';
    wait for 30 ns;
    B<='1';
    wait for 30 ns;
    A<='0';
    wait for 40 ns;
    B<= '0';
    wait for 50 ns;
end process tb;
q<=q_int;
end;