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Altera_Forum
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14 years ago

[Help on VHDL] FATAL ERROR while loading design

Hi guys, I've just started learning VHDL for a week on my own so i'm still very new to it. I'm doing a practice on implementing a 4-bit parallel-out serial shift register.. My codings can be complied...
Altera_Forum's avatar
Altera_Forum
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14 years ago

why have you declared a std_logic_vector of only 1 bit? you really should give it a fixed length, otherwise its really just a std_logic

If you need to change the value during simulation, you should write a testbench.

Your post here is not very clear. If you have a 4 bit output, you need to connect all 4 bits to something.