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Altera_Forum's avatar
Altera_Forum
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16 years ago

help needed!!!

I am trying to do my assignment, I got this error in my port map Error (10500): VHDL syntax error at FA.vhd(34) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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The is keyword in component declaration is optional. As said, the error is in component instantiation. It simply misses instance names. 

regainst: RegA port map( dataA,ldA,clk,rst,Ain);

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Istance names missing is one of the errors. Ports declaration are also needed to be added. The fellowing information is I got after adding instance names. I think checking several times after constructing programme could greatly avoid those errors. 

** Error: E:/modelsim_prog/du.vhd(69): (vcom-1136) Unknown identifier "e1_out".
** Error: E:/modelsim_prog/du.vhd(70): (vcom-1136) Unknown identifier "e2_out".
** Error: E:/modelsim_prog/du.vhd(71): (vcom-1136) Unknown identifier "m1_out".
** Error: E:/modelsim_prog/du.vhd(72): (vcom-1136) Unknown identifier "m2_out".
Good Luck!

Salming