Altera_Forum
Honored Contributor
14 years agoHelp needed for a FPGA begineer
Hi,
I am intending to design a PID controller loop in FPGA for monitoring a stable current . I am quite new in the FPGA world so I need help in the following issues: 1) My loop cycle frequency is 75-90 MHz. I believe I would need ADC and DACs since FPGA is a digital system. I was wondeing if there is any Altera FPGA devices that has built-in ADCs and DACs with that high sample rate(my ADC might have to upsample as well). 2. I need a noise rejection of 60 db, is it feasible to realise in FPGA. As a begineer, I am not sure which device family to look at, any help would be appreciated. Thanks