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Altera_Forum's avatar
Altera_Forum
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14 years ago

help me Verilog problem

I have just study verilog HDL so I found some difficult about it. Can you help me this problem. Tye Net Wand and Wor, I read some books say that they synthesize to AND and OR logic gate, others s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Instead of rescheduling a copy of your previous post,you should try to phrase a clearer question.

wand is a standard Verilog language element, but what is buff?

As a general point, drive strength like weak0 is ignored in synthesis. Refer to the Quartus Verilog HDL support information.