Forum Discussion
Altera_Forum
Honored Contributor
15 years agobut I have a syntax error when I'm compiling some verilog source (few lines) in a .vhd file !
The smart way, is to translate my few verilog lines to vhdl code..but I have a syntax error when I'm compiling some verilog source (few lines) in a .vhd file !
The smart way, is to translate my few verilog lines to vhdl code..