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Honored Contributor
Honored Contributorhelp me to translate verilog to vhdl
hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_ForumHonored Contributor
Honored ContributorWhat are you trying to achieve? VHDL code should be placed in *.vhd files, Verilog code in *.v. Both can be used together in a design.
