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Honored Contributor
Honored Contributorhelp me to translate verilog to vhdl
hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- yes...it's also verilog..did u mean that it can't be converted??? --- Quote End --- That's not the question. In case that the modules are tested ( should be used without modifications) I would not convert them to VHDL. You have to rerun all the testing again and compare it with the old results. That could be very time consuming, especially in case that the submodules are very complex.
