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Altera_Forum's avatar
Altera_Forum
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17 years ago

help me to translate verilog to vhdl

hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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yes...it's also verilog..did u mean that it can't be converted???

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That's not the question. In case that the modules are tested ( should be used without modifications) I would not convert them to VHDL. You have to rerun all the testing again

and compare it with the old results. That could be very time consuming, especially in case that the submodules are very complex.