Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ---------------------------------------------------------------- one input port varaarayin is declared as a type of VARIABLEARRAY. & one output port vararrayout is also declared as a type of VARIABLEARRAY. ----------------------------------------------------------------- I need a equivalent code for this because verilog didnt support 2-D array as input or output port.am i correct? -------------------------------------------------------------------

--- Quote Start --- Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ---------------------------------------------------------------- one input port varaarayin is declared as a type of VARIABLEARRAY. & one output port vararrayout is also declared as a type of VARIABLEARRAY. ----------------------------------------------------------------- I need a equivalent code for this because verilog didnt support 2-D array as input or output port.am i correct? ------------------------------------------------------------------- --- Quote End --- Hi, can you explain what you mean with a 2-D Array input/output ? GPK

@GKP, I am explaining with the help of example. e.g. variablearray is array (1 to nbrvarible_ct+10 ) of slv32; the equivalent memory space occupy by this 2-D array in terms of 1-D array is... var1[(NBRVARIBLE_CT+10)*32:0] ;//here var1 is the array of (NBRVARIBLE_CT+10) locations & the each location of this array is of 32 bit wide.. I hope this is the proper explaination for you.

--- Quote Start --- @GKP, I am explaining with the help of example. e.g. variablearray is array (1 to nbrvarible_ct+10 ) of slv32; the equivalent memory space occupy by this 2-D array in terms of 1-D array is... var1[(NBRVARIBLE_CT+10)*32:0] ;//here var1 is the array of (NBRVARIBLE_CT+10) locations & the each location of this array is of 32 bit wide.. I hope this is the proper explaination for you. --- Quote End --- Hi, you would like to define a memory ? reg [7:0] mem [15:0] // defines a 16x8 memory , Data width 16 bit, Address width 8bit Kind regards GPK

Hi, Dear GKP, exectly same thing as you wrote.but i think,we cant declare the port variable like that // reg [7:0] mem [15:0] // as 2-D array.in verilog. can you suggest me some alternative for that.. Regards, Manoj

--- Quote Start --- Hi, Dear GKP, exectly same thing as you wrote.but i think,we cant declare the port variable like that // reg [7:0] mem [15:0] // as 2-D array.in verilog. can you suggest me some alternative for that.. Regards, Manoj --- Quote End --- Now I'm a little bit confused. Are talking about input or output port of a module ? Kind regards GPK

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Altera_Forum

Honored Contributor

17 years ago

Help me in translation of VHDL to verilog

Hello!

How can i convert a two-dimentional output & input port of vhdl into a verilog.

vhdl:

type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32;

----------------------------------------------------------------

one input port varaarayin is declared as a type of VARIABLEARRAY.

& one output port vararrayout is also declared as a type of VARIABLEARRAY.

-----------------------------------------------------------------

I need a equivalent code for this because verilog didnt support 2-D array as input or output port.am i correct?

-------------------------------------------------------------------

12 Replies

Altera_Forum
Honored Contributor
17 years ago
There is an example that might help you here

http://www.altera.com/support/examples/verilog/ver_bidirec.html

In fact

http://www.altera.com/support/examples/verilog/verilog.html

Has a lot of good examples of Verilog coding that might be of interest to you.

Hope it is what you want
Altera_Forum
Honored Contributor
17 years ago
In case you don't really need a bidirectional wire but have declared this signal as inout because of the VHDL readback restrictions then you just can declare the signal as reg in Verilog.

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Help me in translation of VHDL to verilog

12 Replies

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