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Honored Contributor

17 years ago

Help me in translation of VHDL to verilog

Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...

Altera_Forum

Honored Contributor

17 years ago

In case you don't really need a bidirectional wire but have declared this signal as inout because of the VHDL readback restrictions then you just can declare the signal as reg in Verilog.

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Help me in translation of VHDL to verilog

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