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Altera_Forum
Honored Contributor
Honored ContributorHelp me in translation of VHDL to verilog
Hello! How can i convert a two-dimentional output & input port of vhdl into a verilog. vhdl: type VARIABLEARRAY is array (1 to NBRVARIBLE_CT+10 ) of SLV32; ----------------------------...
Altera_ForumHonored Contributor
Honored ContributorThere is an example that might help you here
http://www.altera.com/support/examples/verilog/ver_bidirec.html In fact http://www.altera.com/support/examples/verilog/verilog.html Has a lot of good examples of Verilog coding that might be of interest to you. Hope it is what you want
