Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHelp defining Global Clock Signals
I am building a DSP structure for a Cyclone III and I am using Quartus II and Verilog to design it. I am trying to be as modular as possible. The design is also as synchronous as it can be. This DSP ...
Altera_ForumHonored Contributor
Honored ContributorQuartus puts clocks onto globals very quickly. Only under extreme conditions(like more clocks than globals or perhaps a clock with a small fanout, such as less than 10) might it not do this. The most important thing is that you have timing constraints in the .sdc describing the clocks. As long as you do that, then however the design is routed, it will be analyzed. Heck, if all the clocks were using local routing and it passed timing, then there shouldn't be any problems.
Do you have gated clocks in your design? Besides that, I doubt clocks are the issue. (And if you do have gated clocks, the problem is not whether or not they're on globals, but that they're constrained correctly)
