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Honored Contributor
Honored ContributorHelp about Verilg error 10663
I got some source code, if I directly compile it without any change, the compilation is successful. If I make any change, even just delete one space in the comments part, and compile it again, it wil...
Altera_ForumHonored Contributor
Honored ContributorAccording to Verilog port connection rules, the sink of a port assignment has to be of the net type. In so far, it's a syntax error to connect an output port to a variable type (e.g. a reg). So the only dubious point is, that the syntax error doesn't show from the beginning.
