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Altera_Forum's avatar
Altera_Forum
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18 years ago

help about cycloneII sdr sdram

I'm having a rather odd problem and I was wondering whether anyone else has experienced it.

I'm using a sdram chip(MT48LC4M16A2-75) in my project.The FPGA is EP2C20Q240C8. In fact we reused the schematics from a previous project and repinned the FPGA. The only difference is that it's a Cyclone II instead of a Cyclone part.

When I run the programme in the sdram ,it always show "verify failded".Are there any diffrences between cycloneII and cyclone?

There are no problem on the physical board.

Thanks for your help.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Sorry, I don't know about the differences between Cyclone and Cyclone II according to sdr sdram, but I also use a sdr sdram with a Cyclone II FPGA.

    I got this error "verify failed", when I didn't give a delay to the clock for the sdram. Between the clock for the sdram controller and the sdram, there should be a delay of 90 degree or some ns.

    If this might be your problem, also check out "Quartus II Handbook Volume 5: Embedded Peripherals -> Section I. Memory Peripherals -> Chapter 1. SDRAM Controller Core" for more information.

    (download here: http://www.altera.com/literature/quartus2/lit-qts-peripherals.jsp)

    Hope this helped.