help about cycloneII sdr sdram

Sorry, I don't know about the differences between Cyclone and Cyclone II according to sdr sdram, but I also use a sdr sdram with a Cyclone II FPGA.

I got this error "verify failed", when I didn't give a delay to the clock for the sdram. Between the clock for the sdram controller and the sdram, there should be a delay of 90 degree or some ns.

If this might be your problem, also check out "Quartus II Handbook Volume 5: Embedded Peripherals -> Section I. Memory Peripherals -> Chapter 1. SDRAM Controller Core" for more information.

(download here: http://www.altera.com/literature/quartus2/lit-qts-peripherals.jsp)

Hope this helped.