Honored Contributor
Honored ContributorOk. Well, I used an example in my text book to write vhdl for the counter. I used the example of code for a state machine. When I got up to the part of the process when you must "Start Simultation", I entered the end time and grid time for the .vwd file and entered the clock input and q outputs by using Node Finder. However, the example in my book shows that "State" was an assignment also, but the node finder shows state.s0, state.s1, and so forth, instead of showing just "State." I guess the tricky part started with the Node Finder. Ask me whatever you need to know, and I can tell you. Thanks for your time and concern.
