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Altera_Forum
Honored Contributor
14 years agothank you ,
I use the avalon bus,but it is not pin to FPGA. xilinx use the dual RAM,one port connect blaze ,the other connect FPGA. how about nios2? for example: I want to do this always @(posedge clkin) begin case(nios_address) 0: reg_a <= nios_dat; 1: reg_b <= nios_dat; ........ endcase end