HDMI/DVI Tx in Cyclone III family device

Question

Hi all,

The idea is to embed a HDMI transmitter inside the Cyclone 3 FPGA. I need to investigate electrical/logical interfaces as well as any needed IP core or driver support. Xilinx offers embedded electrically-compliant TMDS I/O pins in their Spartan 6 family allowing implementation of DVI and HDMI interfaces inside the FPGA. The possibility to perform the same thing in Altera Cyclone is not very clear. At least in the documents I have read (among which: White paper // Using Cyclone III FPGAs for Clearer LCD HDTV Implementation). One of challenges is that HDMI needs up to 10.6 Gbps bitrate @ 350 MHz while Cyclone III can achieve up to 875 Mbps (in their high-speed I/O banks).

There still some other possibilities say connecting a daughter card to the HSMC connector to work as either DVI or HDMI transmitter.

My FPGA board will perform some video processing function on variable resolution video streams (up to 720p @ 60 Hz), then send the streams over TMDS to a high definition monitor with HDMI connector.

My questions are:

- Is it theoretically possible to send such streams without any compression if I am using TMDS protocol?

- Can I just use a DVI Tx in my board, then somehow do a DVI2HDMI conversion?

- Is it possible to use Cyclone´III high-speed I/O banks (primarily designed for differential interfaces like LVDS) for HDMI Tx interface? Are there any electrical constraints? (As you have already noticed I don't need to achieve the HDMI max bitrate, I can survive with much less than that)

- Do I need to have an IP core for TMDS encoding? If so, does Altera provide it?

- Is there any other aspect I have to consider?

This is an industrial project. An expert recommendation will be very appreciated.

altera_forum · Answer

--- Quote Start ---

One of challenges is that HDMI needs up to 10.6 Gbps bitrate @ 350 MHz while Cyclone III can achieve up to 875 Mbps (in their high-speed I/O banks).

--- Quote End ---

I'm unable to relate this statement to the HDMI specification. I wonder where you got it from? The HDMI physical layer is covered by Cyclone 3 LVDS transmitters as far as I see.

altera_forum · Answer

--- Quote Start ---

Implementation). One of challenges is that HDMI needs up to 10.6 Gbps bitrate @ 350 MHz while Cyclone III can achieve up to 875 Mbps (in their high-speed I/O banks).

--- Quote End ---

The HDMI 1.3 spec has a maximum clock rate of 340 MHz with 3 data channels and 10 bits per channel, that gives you 10.2 Gbps. But that is at the highest resolution. If your maximum resolution is 720p, your clock will be 74.25 MHz for a total of 2.23 Gbps transfer, or 742.5 Mbps per lane. This is doable in the Cyclone 3.

--- Quote Start ---

- Is it theoretically possible to send such streams without any compression if I am using TMDS protocol?

--- Quote End ---

Yes

--- Quote Start ---

- Can I just use a DVI Tx in my board, then somehow do a DVI2HDMI conversion?

--- Quote End ---

Yes. There are DVI to HDMI cables readily available online DVI just doesn't have the sound and advanced features of HDMI..

--- Quote Start ---

- Is it possible to use Cyclone´III high-speed I/O banks (primarily designed for differential interfaces like LVDS) for HDMI Tx interface? Are there any electrical constraints? (As you have already noticed I don't need to achieve the HDMI max bitrate, I can survive with much less than that)

--- Quote End ---

You should be able to make it work at 720p. I haven't looked into the other electrical constraints to say for sure however.

--- Quote Start ---

- Do I need to have an IP core for TMDS encoding? If so, does Altera provide it?

--- Quote End ---

Yes you need a TDMS encoder, I'm not aware of any Altera core for this, but they do have some image processing cores, so I wouldn't be surprised if they have one. However the specification is available: http://www.ddwg.org/lib/dvi_10.pdf so it wouldn't be too hard to create it if you need it.

--- Quote Start ---

- Is there any other aspect I have to consider?

--- Quote End ---

Synchronization between clock domains and making sure your clocks/pll's are setup correctly are always concerns. .If you can get it running in a dev board before you spin your board,

I'm a FPGA/ASIC consultant with video and RF DSP experience, so if you need assistance implementing the design, we can help you out. We also have board design and software engineers on staff. If you are interested feel free to message me through this forum.

Regards,

Pete

altera_forum · Answer

I was in fact referring to a standard speed (category 1) HDMI link with 74.25 MHz maximum clock frequency, which is doable without Gbit transceivers.

altera_forum · Answer

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The HDMI physical layer is covered by Cyclone 3 LVDS transmitters as far as I see.

--- Quote End ---

Do you have any reference for this? Reference design or a link? This would things much easier..

The question is: Can TMDS be physically interfaced by LVDS?

altera_forum · Answer

--- Quote Start ---

The HDMI 1.3 spec has a maximum clock rate of 340 MHz with 3 data channels and 10 bits per channel, that gives you 10.2 Gbps. But that is at the highest resolution. If your maximum resolution is 720p, your clock will be 74.25 MHz for a total of 2.23 Gbps transfer, or 742.5 Mbps per lane. This is doable in the Cyclone 3.

--- Quote End ---

The Dedicated differential output buffers on side I/O banks support LVDS transmit at up to 840 Mbps. Is that is why you suggest that sending 720p frame is doable in Cyclone III?

Apart from that, I'm still a bit confused about I/O pin speed. The fpga specification give the throughput per pin, and not per channel/lane, right?

Another thing, the throughput that the specification gives depends upon the max frequency the fpga could support, right?

That's said, is it possible to calculate the min I/O pins speed I would need for example to use TMDS protocol for a given resolution?

Sorry for all of this confusion, but I'm rather beginner then an expert. I can't sleep at night trying to find answers for these questions.

--- Quote Start ---

Yes you need a TDMS encoder, I'm not aware of any Altera core for this, but they do have some image processing cores, so I wouldn't be surprised if they have one. However the specification is available: http://www.ddwg.org/lib/dvi_10.pdf so it wouldn't be too hard to create it if you need it.

--- Quote End ---

--- Quote Start ---

I'm a FPGA/ASIC consultant with video and RF DSP experience, so if you need assistance implementing the design, we can help you out. We also have board design and software engineers on staff. If you are interested feel free to message me through this forum.

Regards,

Pete

--- Quote End ---

Thanks Pete for your detailed answer. I will contact u if i hear anything from my manager. There is also this encryption part in HDMI. Is it smthg i have to consider? We won't need any kind of encryption for this application.

//Update:

We need help with a MJPEG or H264 encoder that can handle 1080p @ 60Hz. If you think you can help us with that we can discuss further price and target technology. Footprint should be minimum for Cyclone III, EP3C10.

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HDMI/DVI Tx in Cyclone III family device

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