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Altera_Forum
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15 years ago

Hardware VS Software

I am doing some performance analysis for hardware and software. The program will generate a set of random 32 bits number. these numbers will be send to a user peripheral (hardware) for addition. then...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

an example multiply entity - no problems compiling in quartus: 


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity my_mult is
  port (
    
    clk     : in  std_logic;
    
    a,b     : in  unsigned( 7 downto 0);
    c       : out unsigned(15 downto 0)
  )
end entity;
  
architecture rtl of my_mult is
begin
  
  process(clk)
  begin
    if rising_edge(clk) then
      c <= a*b;
    end if;      
  end process;
  
end rtl;