Hardware connection to FPGA

If I understood You correctly, You want to create a bidirectional port. There, You must create a tri-state buffer. It may look something like this:

Port : inout std_logic_vector (2 downto 0);

And then in architecture section you must define tri-state buffer:

Port <= Port_out when Out_enable = '1' else (others => 'Z');

If You want to use Port as output You must turn Out_enable signal to '1'. Otherwise it will work as input.

Hope I made it clear to You :)