Hard Copy ASIC for MAX 10 FPGA Design

I am interested in getting hardcopy ASIC out of MAX10 FPGA implemented design. The proof of concept is validated in MAX10 FPGA & for production the volume can be around 10K units. The processing engine that goes into the device is a low power handheld device. So, getting a hardcopy ASIC would be beneficial for low power as well as cost of manufacturing ASICs.

From the below document, I see stratix FPGA & hardcopy IV share same IP cores thus can be interchangeable.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/po/ss-hcasics.pdf

Is Hardcopy ASIC possible with MAX10 FPGAs?

Regards,

Ritesh