Handling large arrays in VHDL

Regarding the original problem, how to scan the content of a 256x16 table.

A result in one clock cycle can be only achieved by the two solutions mentioned in your post. Alternatively you can implement a binary search tree, that finds the result in 8 steps (8 clock cycles) in a 256x16 ROM table. The method is very similar to the operation of a succesive approximation ADC.

Hybrid methods using multiple small tables and 2 or 3 clock cycles should be possible as well.